FlowCV Logo
resume profile picture
Hemanth Nag Chopparapu
Email
[email protected]
Location
Vijayawada ,Andhra Pradesh
LinkedIn
Linkedin
Carrier Objective

Aspiring to leverage my experience in FPGA development, VLSI design, and embedded systems in a dynamic engineering role, focusing on hardware optimization and real-time data processing. Seeking to contribute to projects that make change.

Education
B.Tech in Electronics and Communication Engineering, KL University

CGPA: 9.58 (currently)

2021 Sep – presentGuntur, India
Intermediate MPC, Sri Viswasanti Junior College

MARKS:714

2019 – 2021Vuyyuru, india
Secondary Education (X),Sri Viswasanti Educational Institution

MARKS:404(CBSE)

2019Vuyyuru, India
Skills
Programming Languages:

Verilog, C, Python (basic), java

Hardware:

FPGA, Lora Modules, NI ELVIS, Arduino, Raspberry Pi, Node MCU, ESP32

Tools:

Cadence, Xilinx Vivado, Matlab, Dire-Wolf, NI-Multisim,Altium Designer

soft skills:

Critical Thinking, Effective Communication, Adaptive Learner, Public Speaker

Cetifications
System verilog and UVM, Tessolve Semiconductors
Workshop about Revolutionizing Tomorrow(IIIT Sricity), Exploring Cutting Edge Trends in Integrated Circuit
Amature Radio License, United States of America Federal Communications Commission
Business English Certificate Preliminary, Cambridge International Education
Professional Experience
Project Intern, National Remote Sensing Centre-ISRO
  • •Engineered a PLL-based clock recovery loop for high-speed data transmission.

    • • Gained hands-on experience with MATLAB Simulink and Verilog in Xilinx Vivado

    2023 May – 2023 JunShadnagar, India
    Virtual Intern, Tessolve Semi Conductors

    • Created and optimized Verilog code for high-performance VLSI circuits, focusing on timing and resource constraints.

    Projects
    Hardware-Efficient CNN-based Object Detection for video surveillance applications (ONGOING)
  • •Integrating machine learning with FPGA for real-time object detection in video surveillance
  • •Applying hardware optimization for a low-power, real-time detection solution.
    • Implementation of Hardware Efficient FPGA-Based Edge Detection of Various Objects
  • •Developed FPGA-based edge detection using Canny, Sobel, and Prewitt algorithms.
  • •Utilized the ZedBoard Zynq for real-time performance analysis.
    • KLSAT (KL Satellite)

    • Designed and integrated 1U Cubesat Module for launch via High Altitude Balloon.

    • Contributed to communication, telemetry, software coding, hardware integration, and testing.

    Design and Analysis of CCII

    • Designed and analyzed Current Conveyor II (CCII) circuits using Cadence Virtuoso.

    • Implemented and simulated CCII circuits to assess performance metrics.

    PUBLICATIONS AND ACHIEVEMENTS
  • •Published patent holder for ”Hardware Applications Accelerated Edge Detection on FPGA Platforms for Embedded Vision.”

    • • Awarded a certificate for the successful launch of KLSAT-KLSATellite by KL University, presented by Mr. Vinod Kumar, IAS, Managing Director, APSSDC, Government of Andhra Pradesh

  • •Runner-up in “IDOL OF ECE” by the department of ECE, KL University.
    • Linguistic Proficiency
    English , Telugu , Hindi ,Japanese(N5)