Abdallah Mohamed Roshdy
Email
[email protected]
Location
Al-Haram.St-Giza-Egypt
Phone
(+20) 100-725-5863
Exempted from military service
Objective
working on myself every day to cope with the progress in the communications and technology field, seeking important and big role in a multinational company.
Education

BSc. Of Communication and Electronics, Faculty of Engineering Sep 2017 – Jul 2022 Mansoura University Accumulative Grade: Very good with honors (84%) Graduation Project : Automobile security based on face recognition Project grade : Excellent

Professional Experience

Front Office Engineer

Huawei, GNOC
  • •Conducted 24/7 network surveillance for RAN, Core, and Transmission domains.
    • 2025/06 – PresentCairo , Egypt
  • •Analyzed alarms, identified root causes, and executed remote corrective actions when possible.
  • •Managed trouble tickets and incident workflows using Huawei OWS tools.
  • •Coordinated with field engineers for on-site interventions and ensured timely fault rectification.
  • •Supported performance optimization by tracking KPIs and highlighting degradations.

    • Mobile Package (GSM, GPRS, EDGE, UMTS, HSDPA, HSUPA, HSPA+, LTE, LTE Advanced pro)

    Ditgital Design and ASIC Implementation Intern

    Si-Vision, Q4E Program

    Skills: CDC, STA, Low Power, DFT, Synthesis, Formality, PnR, FPGA Prototyping, Design with verilog and systemVerilog, Scripting Languages

    2023/12 – 2024/07Cairo, Egypt

    Tools: Synopsys Tools

    Final Project: RTL2GDS11 - Design and Implemetation of SPI Digital System transmitter

    9-Month Professional Diploma, Information Technology Institute (ITI) Ministry of Communications and Information Technology (MCIT)

    2022/10 – 2023/07
    Courses

    CCNA 200-301

    CCNP Encore 350-401

    Technical Skills
    Linux

    Red Hat Admin 1

    Programming Languages

    C , C++ ,Python and Embedded C

    Hardware Description language

    Verilog and VHDL

    Scripting languages

    TCL

    Tools

    Modelsim , Vivado and Cadence

    ASIC Flow

    Synthesis, DFT,Floorplanning, Powerplanning, Placement , Routing, CTS , STA.

    Projects

    Pipelined 32-bit RISC-V Processor.

    Design & implementation of a 5-stage partial pipelined processor (datapath and control logic) with a hazard unit in Verilog. Tested using an assembly program.

    Full-custom design of a 4:16 decoder Designed and verified using Cadence Virtuoso.

    FPGA-based bank SBqM system Using Verilog.

    Languages
    Arabic (Mother tongue)
    English