Le Viet CuongDesign Implementation Engineer
Profile

Electronics and Telecommunications Engineering graduate from Ho Chi Minh City University of Technology, seeking a fresher role as a Design Implementation Engineer. Skilled in RISC-V processor design, TCAM optimization, and digital IC implementation. Proficient with industry standard EDA tools and motivated to contribute to innovative semiconductor projects while enhancing technical expertise.

Education
Ho Chi Minh City University of Technology, Bachelor of Electronics and Telecommunications Engineering
09/2021 – 08/2025Ho Chi Minh, Vietnam
  • •GPA: 3.1/4.0
  • •Relevant Coursework: Digital System Design, VLSI Design, Computer Architecture, Microelectronics.
    • Professional Experience
    Ampere Computing Vietnam, Technical Intern
    06/2025 – Present
  • •Investigated the design flow from logical synthesis to end of placement and routing.
  • •Studied the fundamental concepts of Static Timing Analysis (STA) and their role in timing closure.
  • •Learned about SDC and practiced applying them for timing validation.
  • •Analyzed reports to identify design issues and possible fixes.
  • •Prepared and delivered weekly presentations to the team, sharing progress and key learnings.
    • Projects
    IMPLEMENTING INTERRUPT HANDLER FOR RISC-V ISA
    09/2024 – 06/2025
  • •Designed a 5-stage pipeline CPU with 90% branch prediction accuracy, reducing stalls and enhancing performance.
  • •Optimized the CPU for 50 MHz operation, showcasing expertise in high-performance computing.
  • •Developed an APB system for efficient CPU-peripheral communication (Timer, UART, GPIO).
  • •Designed an interrupt controller to manage multiple peripheral interrupts.
  • •Developed Timer and UART IPs, ensuring MCU compatibility and essential operational modes.
  • •Synthesized CPU and IPs using Cadence Genus, using clock gating method to optimize PPA.
  • •Deployed the system on a DE2 FPGA, integrating custom-designed IPs.
  • •Conducted performance testing to analyze latency, resource usage, and scalability.
    • DON'T CARE GATING TCAM
    02/2024 – 05/2024
  • •Analyzed 4 TCAM types, identifying Don't Care Gating TCAM as the optimal low-power solution (30% power reduction).
  • •Designed and simulated a 8×8 TCAM array in Cadence Virtuoso, achieving 30% lower delay and 25% lower power in search operations.
  • •Validated TCAM design at cell and array levels, optimizing timing and power across operating modes.
    • Technical Skill

    • Hardware Description Languages: Verilog, SystemVerilog.

    • Programming Languages: C, Python, TCL.

    • EDA Tools: Synopsys VCS+Verdi, Cadence Genus, Cadence Virtuoso, Cadence Xcelium, Intel Quartus.

    • Operating Systems: Linux.

    • IC Design Knowlegde: IC Design Flow, AMBA Protocols, Static Timing Analysis, SRAM and TCAM Design, RISC-V Architecture, Digital Signal Processing.

    Soft Skill
  • •Basic proficiency in Microsoft Word, PowerPoint, and Excel.
  • •Strong teamwork and collaboration abilities.
  • •Excellent interpersonal and communication skills.
    • Certificates
    IELTS

    Score: Band 6.5-08/2023 (Listening: 6.5 Reading: 7.5 Writing: 6.5 Speaking: 6.0)